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october 1994 2 philips semiconductors product speci?cation 8-bit microcontrollers with osd and vst 84c44x; 84c64x; 84c84x contents 1 features 1.1 pcf84cxxxa kernel 1.2 derivative features pca84c640 2 general description 2.1 important 3 ordering information 4 block diagram 5 pinning information 6 differences 7 reset 7.1 power-on-reset 8 analog control 8.1 6-bit pwm dacs 8.1.1 pin selection for pwm outputs 8.1.2 polarity of the pwm outputs 8.1.3 analog output voltage 9 vst control 9.1 14-bit pwm dac 9.1.1 14-bit counter 9.1.2 data and interface latches 9.2 coarse adjustment 9.3 fine adjustment 10 afc input 11 input/output ( i/o) 12 on screen display 12.1 features 12.2 horizontal display position control 12.3 vertical display position control 12.4 clock generator 12.4.1 rc oscillator 12.4.2 lc oscillator 12.5 display data registers 12.6 display control registers 12.6.1 derivative register osdca 12.6.2 derivative registers line 0a and line 0b 12.6.3 derivative registers line 1a and line 1b 12.6.4 derivative register osdcb 12.7 osd display position 12.7.1 vertical position 12.7.2 horizontal position 12.8 osd character size and colour selection 12.8.1 character size 12.8.2 colour selection 12.9 character rom 13 emulation mode 14 register map 15 limiting values 16 dc characteristics 17 ac characteristics 17.1 characteristic curves 18 package outline 19 soldering 19.1 plastic dual in-line packages 19.1.1 by dip or wave 19.1.2 repairing soldered joints 20 definitions 21 life support applications 22 purchase of philips i 2 c components
october 1994 3 philips semiconductors product speci?cation 8-bit microcontrollers with osd and vst 84c44x; 84c64x; 84c84x 1 features 1.1 pcf84cxxxa kernel 8-bit cpu, rom, ram, i/o in a single 42 leads shrink dil package over 80 instructions all of 1 or 2 cycles 29 quasi bidirectional standard i/o port lines configuration of i/o lines individually selected by mask external interrupt int/t0 2 direct testable inputs t0, t1 8-bit programmable timer/event counter 3 single level vectored interrupts (external, timer/counter, i 2 c-bus) power-on-reset and low voltage detector single power supply 2 power reduction modes: idle and stop operating temperature range: - 20 to +70 c silicon gate cmos fabrication process (sac2). 1.2 derivative features pca84c640 although the pca84c640 is specifically referred to throughout this data sheet, the information applies to all the devices. the small differences between the 84c640 and the other devices are specified in the text and also highlighted in chapter 6. the pca84c640 comprises: the pcf84cxxxa processor core 6 kbytes mask-programmable program rom 128 bytes ram multi-master i 2 c-bus interface afc input for voltage synthesized tuning (vst; with 3-bit dac and comparator) on screen display (osd) facility for two rows of 16-characters on screen display character set of 64 types four programmable display dot sizes half dot character rounding seven colours for each character one 14-bit pwm output for vst five 6-bit pwm outputs for analog controls eight port lines with 10 ma led drive capability 18 general purpose bidirectional i/o lines plus 11 function-combined i/o lines 2 direct testable lines programmable vsyncn and hsyncn input polarity rc oscillator for osd function. 2 general description the 84c44x; 84c64x; 84c84x denotes the types: pca84c440; 84c441; 84c443; 84c444 pca84c640; 84c641; 84c643; 84c644 pca84c840; 84c841; 84c843; 84c844, which are 8-bit microcontrollers with on screen display (osd) and voltage synthesized tuning (vst) functions. all are members of the 84cxxx microcontroller family. there are two oscillator types for the osd function in the various types, i.e., rc oscillator: pca84c440; 84c443; 84c640; 84c643; 84c840; 84c843 lc oscillator: pca84c441; 84c444; 84c641; 84c644; 84c841; 84c844. 2.1 important note this data sheet details the specific properties of the pca84c44x, pca84c64x and pca84c84x. the shared characteristics of the pca84cxxx family of microcontrollers are described in the pcf84cxxxa family single-chip 8- bit microcontroller of data handbook ic14 , which should be read in conjunction with this data sheet. 3 ordering information type number package temperature range ( c) name description version pca84c440; 84c443; 84c640; 84c643; 84c840; 84c843 sdip42 plastic shrink dual in-line package; 42 leads (600 mil) sot270-1 - 20 to +70 pca84c441; 84c444; 84c641; 84c644; 84c841; 84c844
october 1994 4 philips semiconductors product speci?cation 8-bit microcontrollers with osd and vst 84c44x; 84c64x; 84c84x 4 block diagram fig.1 block diagram. handbook, full pagewidth 84cxxx core excluding rom / ram 8-bit internal bus 8-bit timer / event counter cpu parallel i / o ports rom (1) ram (2) 8-bit i / o ports 6-bit dac 14-bit dac 3-bit dac + comparator i c interface 2 display on screen 5 p0 p1 dp0 dp1 1 2 3 4 5 vob vow1 vow2 vow3 dosc1 dosc2 (3) vsyncn hsyncn test / emu xtal1 (in) xtal2 (out) reset tdac afc sda scl mcd170 t1 int / t0 pwm (4) (5) (6) 8 8 8 (1) 4k bytes for the pca84c440; 84c441; 84c443; 84c444. 6k bytes for the pca84c640; 84c641; 84c643; 84c644. 8k bytes for the pca84c840; 84c841; 84c843; 84c844. (2) 128 bytes for the pca84c440; 84c441; 84c443; 84c444; 84c640; 84c641; 84c643; 84c644. 192 bytes for the pca84c840; 84c841; 84c843; 84c844. (3) for use with an lc oscillator, only available with the: pca84c441; 84c444; 84c641; 84c644; 84c841; 84c844. (4) i 2 c-bus interface not available with the: pca84c443; 84c444; 84c643; 84c644; 84c843; 84c844. (5) dp1.4 only available for pca84c440; 84c443; 84c640; 84c643; 84c840; 84c843. (6) t1 = pin 29 for pca84c440; 84c443; 84c640; 84c643; 84c840; 84c843. t1 = pin 34 for pca84c441; 84c444; 84c641; 84c644; 84c841; 84c844.
october 1994 5 philips semiconductors product speci?cation 8-bit microcontrollers with osd and vst 84c44x; 84c64x; 84c84x 5 pinning information fig.2 pinning diagram for pca84cx40; 84cx43. handbook, halfpage mcd172 1 2 3 4 5 6 7 8 9 10 11 12 13 40 39 38 37 36 35 34 33 32 31 30 29 28 27 14 15 16 17 18 19 20 22 23 24 25 26 21 42 41 dp0.5/pwm5 dp0.4/pwm4 dp0.3/pwm3 dp0.2/pwm2 dp0.1/pwm1 dp0.0/tdac dp1.7/afc p1.0 p1.1 p1.2 p1.3 p1.4 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 v ss dp1.0 dp0.6/sda dp0.7/scl dp1.1 dp1.2 dp1.3 int / t0 dp1.4 xtal2 xtal1 test/emu dosc1 hsyncn vow2/dp1.5 t1 vsyncn vob vow1/dp1.6 vow3 dd v reset pca84c640 pca84c643 pca84c840 pca84c843 pca84c440 pca84c443 handbook, halfpage mcd171 1 2 3 4 5 6 7 8 9 10 11 12 13 40 39 38 37 36 35 34 33 32 31 30 29 28 27 14 15 16 17 18 19 20 22 23 24 25 26 21 42 41 dp0.5/pwm5 dp0.4/pwm4 dp0.3/pwm3 dp0.2/pwm2 dp0.1/pwm1 dp0.0/tdac dp1.7/afc p1.0 p1.1 p1.2 p1.3 p1.4 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 v ss pca84c441 pca84c444 pca84c641 pca84c644 pca84c841 pca84c844 dp1.0 dp0.6/sda dp0.7/scl dp1.1 dp1.2 dp1.3 int/t0 t1 xtal2 xtal1 test/emu dosc1 hsyncn vow2/dp1.5 dosc2 vsyncn vob vow1/dp1.6 vow3 dd v reset fig.3 pinning diagram for pca84cx41; 84cx44.
october 1994 6 philips semiconductors product speci?cation 8-bit microcontrollers with osd and vst 84c44x; 84c64x; 84c84x table 1 pin description note 1. 84cx40; 84cx43 denotes the types: pca84c440, pca84c443, pca84c640, pca84c643, pca84c840 and pca84c843. 84cx41; 84cx44 denotes the types: pca84c441, pca84c444, pca84c641, pca84c644, pca84c841 and pca84c844. symbol (1) pin (1) description 84cx40; 84cx43 84cx41; 84cx44 84cx40; 84cx43 84cx41; 84cx44 deviating pinning dp1.0 to dp1.4 dp1.0 to dp1.3 41, 38, 37, 36, 34 41, 38, 37, 36 derivative port 1: quasi-bidirectional i/o lines. t1 t1 29 34 direct testable pin and event counter input. dosc1 - 28 - connection to rc oscillator of osd clock. - dosc1/dosc2 - 28, 29 connections to lc oscillator of osd clock. mutual pinning dp0.0/tdac 1 derivative port 0: quasi-bidirectional i/o line or 14-bit dac pwm. dp0.1 to dp0.5/pwm1 to pwm5 2 to 6 derivative port 1: quasi-bidirectional i/o lines or 6-bit dac pwm. p1.0 to p1.4 7, 8, 10, 12 port 1: quasi-bidirectional i/o lines. p0.0 to p0.7 13 to 20 port 0: quasi-bidirectional i/o port. dp1.7/afc 9 derivative port 1: quasi-bidirectional i/o line or comparator input with 3-bit dac. dp0.6/sda 40 derivative open drain i/o port or i 2 c-bus data line. dp0.7/scl 39 derivative open drain i/o port or i 2 c- bus clock line. int/t0 35 external interrupt or direct testable line. dp1.5 to dp1.6/vow2 to vow1 23, 22 derivative port 1: quasi-bidirectional i/o lines or character video output. reset 33 initialize input, active low. xtal2, xtal1 32, 31 oscillator output or input terminal for system clock. test/emu 30 control input for testing and emulation mode. ground for normal operation. vsyncn 27 vertical synchronous signal input. hsyncn 26 horizontal synchronous signal input. vob 25 blanking output. vow3 24 character video output of osd. v ss 21 ground. v dd 42 power supply.
october 1994 7 philips semiconductors product speci?cation 8-bit microcontrollers with osd and vst 84c44x; 84c64x; 84c84x 6 differences between the types table 2 differences between the types pca84c44x, pca84c64x and pca84c84x in this table: yes = available; no = not available. feature pca... 84c440 84c441 84c443 84c444 84c640 84c641 84c643 84c644 84c840 84c841 84c843 84c844 osd oscillator rc lc rc lc rc lc rc lc rc lc rc lc general purpose i/o lines 18 17 18 17 18 17 18 17 18 17 18 17 i 2 c-bus interface yes yes no no yes yes no no yes yes no no rom 4 kbytes 6 kbytes 8 kbytes ram 128 bytes 128 bytes 192 bytes pin assignment pin 29 t1 dosc2 t1 dosc2 dp1.4 t1 dp1.4 t1 dp1.4 t1 dp1.4 t1 pin 34 dp1.4 t1 dp1.4 t1 t1 dosc2 t1 dosc2 t1 dosc2 t1 dosc2 register dp1 (bit dp1.4) pin yes no yes no yes no yes no yes no yes no latch yes no yes no yes no yes no yes no yes no
october 1994 8 philips semiconductors product speci?cation 8-bit microcontrollers with osd and vst 84c44x; 84c64x; 84c84x 7 reset the reset pin (active low input) is used to initialize the microcontroller to a defined state. the reset configuration is shown in fig.5. fig.4 external components for reset pin. handbook, halfpage v ss dd v r 100 k w c reset mcd174 7.1 power-on-reset the power-on-reset circuit monitors the voltage level of v dd . if v dd remains below the internal reference voltage level v ref (typically 1.3 v), the oscillator is inhibited. when v dd rises above v ref , the oscillator is released and the internal reset is active for a period of t d (typically 50 m s). considering the v dd rise time, the following measures for a correct power-on-reset can be taken: if the v dd rises above the minimum operation voltage before time period t d is exceeded, no external components are necessary (see fig.6). if v dd has a slow rise time, such that after the time period has elapsed the supply voltage is still below the minimum operation voltage (v min ), external components are required (see figs 4 and 7). to guarantee a correct reset operation, ensure that . a definite power-on-reset can be realized by applying an (external) reset signal during power-on. (t vref t d ) + the time constant rc 8 t vdd 3 fig.5 reset configuration. handbook, full pagewidth mla651 v ss dd v reset power on reset oscillator inhibit ref v internal reset
october 1994 9 philips semiconductors product speci?cation 8-bit microcontrollers with osd and vst 84c44x; 84c64x; 84c84x fig.6 reset with fast rising v dd . handbook, full pagewidth v dd v ss v ref v dd v dd v ss reset oscillator oscillator start up time t d mcd240 handbook, full pagewidth v dd v ss v ref v dd v ss oscillator oscillator start up time t d v min t vref vdd rc 8 t vdd t v dd reset without external component v ss v dd reset with external component mcd241 fig.7 reset with slow v dd .
october 1994 10 philips semiconductors product speci?cation 8-bit microcontrollers with osd and vst 84c44x; 84c64x; 84c84x 8 analog control 8.1 6-bit pwm dacs five pwm outputs are available for analog control purposes e.g. volume, balance, brightness, saturation etc. the block diagram of a typical 6-bit pwm dac is shown in fig.8. each pwm output can generate pulses of programmable length that have a repetition frequency of 1 64 f pwm , where f pwm = 1 3 f xtal . 8.1.1 p in selection for pwm outputs the pwm outputs pwm1 to pwm5 , share the same pins as the derivative port lines dp0.1 to dp0.5 . setting the (relevant pwm enable) bit pwmne to: logic 1, selects the relevant pwmx output function logic 0, selects the relevant dp0.x port function. 8.1.2 p olarity of the pwm outputs the polarity of all five pwm outputs is selected by the state of the polarity control bit p6lvl. setting the control bit p6lvl to: logic 0, sets the pwmx outputs to the default polarity logic 1, inverts all the pwmx outputs. 8.1.3 a nalog output voltage a dc voltage proportional to the pwm control setting may be obtained by connecting an integrating network to each of the pwm outputs (see fig.9). the analog value is calculated as follows: where: pwmdl is the decimal value of the contents of the pwm data latch. therefore, the analog output voltage is: v a t high t r ------------- - v o = t high t 0 pwmdl high time of the pwm puls e = = t r t 0 64 repetition time of the pwm pulse = = t 0 3 f xtal ----------- -- - = v a pwmdl 64 ----------------------- - v o = fig.8 block diagram of the 6-bit pwm dac. handbook, full pagewidth mcd176 dp0.x data i / o dp0.x / pwmx 6-bit pwm data latch p6lvl pwmne 6-bit dac pwm controller q q polarity control bit f pwm
october 1994 11 philips semiconductors product speci?cation 8-bit microcontrollers with osd and vst 84c44x; 84c64x; 84c84x fig.9 pwm output patterns (p6lvl = 0). handbook, full pagewidth mcd175 00 01 m 63 f pwm 2 decimal value pwm data latch 64 1 3 m m+1 m+2 63 64 1 t 0
october 1994 12 philips semiconductors product speci?cation 8-bit microcontrollers with osd and vst 84c44x; 84c64x; 84c84x 9 vst control 9.1 14-bit pwm dac the pca84c640 has one 14-bit pwm dac output (tdac) with a resolution of 16384 levels for voltage synthesized tuning. the pwm dac (see fig.10) consists of: 14-bit counter two 7-bit dac interface data latches (vsth and vstl) one 14-bit dac data latch (vstreg) pulse control. the polarity of output tdac is selected with bit p14lvl. setting the bit p14lvl to: logic 1, sets the tdac output to the default polarity logic 0, inverts the tdac output. 9.1.1 14- bit counter the counter is continuously running and is clocked by f 0 . the period of the clock, the repetition time for one complete cycle of the counter: the repetition time for one cycle of the lower 7-bits of the counter is: therefore, the number of t sub periods in a complete cycle t r is: 9.1.2 d ata and interface latches in order to ensure correct operation, interface data latch vsth is loaded first and then interface data latch vstl. the contents of: vsth are used for coarse adjustment vstl are used for fine adjustment. at the beginning of the first t sub period following the loading of vstl, both data latches are loaded into data latch vstreg. after the contents of vsth and vstl are latched into vstreg, one t sub period is needed to generate the appropriate pulse pattern. to ensure correct dac conversion, two (2) t sub periods should be allowed before beginning the next sequence. t 0 3 f xta l ------------- - = t r t 0 16 38 4 = t sub t 0 128 = n t 0 16 384 t 0 128 --------------------------- 128 = = 9.2 coarse adjustment the coarse adjustment output (out1) is reset to low (inactive) at the start of each t sub period. it will remain low until the time has elapsed and then will go high and remain so until the next t sub period starts. 9.3 fine adjustment fine adjustment is achieved by generating additional pulses at the start of particular sub-periods (t subn ). these additional pulses have a width of t 0 . the sub- period in which a pulse is added is determined by the contents of vstl interface latch. table 3 gives the numbers of the t subn , at the start of which an additional pulse is generated, depending on the bit in vstl being a logic 0. when more than one bit is a logic 0 a combination of additional pulses are generated. for example, if vstl = 1111010, which is a combination of vstl = 1111110: sub-period 64, and vstl = 1111011: sub-periods 16, 48, 80, 112, then additional pulses will be given in sub-periods 16, 48, 64, 80 and 112; this is illustrated in fig.12. if vsth = 0011101, vstl = 1111010 and p14lvl = 0, then the tdac output is as shown in fig.13. table 3 additional pulse distribution lower 7 bits (vstl) additional pulse in sub-periods t subn 111 111 0 64 111 11 0 1 32, 96 111 1 0 11 16, 48, 80, 112 111 0 111 8, 24, 40, 56, 72, 88, 104, 120 11 0 1111 4, 12, 20, 28, 36, 44, 52, 60 .... 116, 124 1 0 1 1111 2, 6, 10, 14, 18, 22, 26, 30, .... 122, 126 0 11 1111 1, 3, 5, 7, 9, 11, 13, 15, 17, .... 125, 127 t 0 vsth 1 + ( ) [ ]
october 1994 13 philips semiconductors product speci?cation 8-bit microcontrollers with osd and vst 84c44x; 84c64x; 84c84x handbook, full pagewidth data latch vstl data latch vsth dac data latch vstreg "mov instruction" "mov instruction" data load timing pulse coarse pwm fine out2 out1 add q q p14lvl 14-bit counter q14 - 8 q7 - 1 polarity control bit tdac output f 0 mcd177 7 7 7 7 load fig.10 block diagram of the 14-bit pwm dac. fig.11 coarse adjustment output (out1). handbook, full pagewidth t r t sub0 out 1 t sub1 t subn t sub127 t x (vsth+1) 0 mcd313
october 1994 14 philips semiconductors product speci?cation 8-bit microcontrollers with osd and vst 84c44x; 84c64x; 84c84x fig.12 fine adjustment output (out2). handbook, full pagewidth mcd314 t sub0 t sub16 t sub32 t sub48 t sub64 t sub80 t sub96 t sub112 t sub127 t r 111 1110 111 1101 111 1011 111 1010 vstl fig.13 tdac output. handbook, full pagewidth mcd315 t r t sub0 out 1 out 2 tdac t sub16 t sub32 t sub48 t sub64 t sub80 t sub96 t sub112 t sub127
october 1994 15 philips semiconductors product speci?cation 8-bit microcontrollers with osd and vst 84c44x; 84c64x; 84c84x 10 afc input the afc input is used to measure the level of the automatic frequency control signal. this is achieved by comparing the afc input signal with the output of a 3-bit dac as shown in fig.14. dac analog switches select one of 8 resistor taps connected between v dd and v ss . consequently, eight different voltages may be selected (see table 4). the compare signal afcc, can be tested to determine whether the afc input is higher or lower than the dac level. the afc input shares the same pin as the derivative port line dp1.7. setting the enable bit afce to: logic 1, selects the afc function logic 0, selects the derivative port dp1.7 function. table 4 selection of v ref afc2 afc1 afc0 v ref v ref (for v dd = 5.0 v) 0 0 0 v dd 0.125 0.625 v 0 0 1 v dd 0.250 1.250 v 0 1 0 v dd 0.375 1.875 v 0 1 1 v dd 0.500 2.500 v 1 0 0 v dd 0.625 3.125 v 1 0 1 v dd 0.750 3.750 v 1 1 0 v dd 0.875 4.375 v 1 1 1 v dd 5.000 v handbook, full pagewidth comparator 3-bit dac en en dp1.7 / afc afc2 afc1 afc0 afce afcc internal bus inner latches dp1.7 mcd178 fig.14 afc circuit.
october 1994 16 philips semiconductors product speci?cation 8-bit microcontrollers with osd and vst 84c44x; 84c64x; 84c84x 11 input/output (i/o) each parallel i/o port line may be individually configured using one of three possible i/o mask options. the three i/o mask options are specified below: option 1 standard port with switched pull-up current source, fig.15. option 2 open drain, fig.16. option 3 push-pull (output only), fig.17. table 5 specifies the possible port option list. when these devices are used for emulation purposes, in order to match the piggy back device provided it is recommended that the port options listed in table 6 are used. handbook, full pagewidth mla696 tr3 i/o port line slave d sq sq master d mq write pulse outl / orl / anl / mov data bus orl / anl / mov in / mov tr1 v ss tr2 v dd constant current source 100 m a typ. fig.15 standard output with switched pull-up current source (option 1). handbook, full pagewidth mla697 i/o port line slave d sq sq master d mq write pulse outl / orl / anl data bus orl / anl in tr1 v ss v dd fig.16 open drain type i/o (option 2).
october 1994 17 philips semiconductors product speci?cation 8-bit microcontrollers with osd and vst 84c44x; 84c64x; 84c84x handbook, full pagewidth mlb998 tr3 output line slave d sq sq master d mq write pulse outl / orl / anl data bus orl / anl in tr1 v ss tr2 v dd constant current source 100 m a typ. fig.17 push-pull type output (option 3).
october 1994 18 philips semiconductors product speci?cation 8-bit microcontrollers with osd and vst 84c44x; 84c64x; 84c84x table 5 user mask programmable port option list notes 1. each pin can be configured to a high (s) or low (r) state after power-on-reset. the required state of each pin is therefore specified by r or s. 2. dp1.4 available only with the pca84c440, pca84c443, pca84c640, pca84c643, pca84c840 and pca84c843. port pin option (1) p0.0 13 p0.1 14 p0.2 15 p0.3 16 p0.4 17 p0.5 18 p0.6 19 p0.7 20 p1.0 7 p1.1 8 p1.2 10 p1.3 11 p1.4 12 dp0.0 1 dp0.1 2 dp0.2 3 dp0.3 4 dp0.4 5 dp0.5 6 dp0.6 40 dp0.7 39 dp1.0 41 dp1.1 38 dp1.2 37 dp1.3 36 dp1.4 (2) 34 dp1.5 23 dp1.6 22 dp1.7 9 vob 25 3 r vow3 24 3 r table 6 port options for the 84c640 in emulation mode port pin option p0.0 13 1 s p0.1 14 1 s p0.2 15 1 s p0.3 16 1 s p0.4 17 1 s p0.5 18 1 s p0.6 19 1 s p0.7 20 1 s p1.0 7 1 s p1.1 8 1 s p1.2 10 1 s p1.3 11 1 s p1.4 12 1 s dp0.0 1 dp0.1 2 dp0.2 3 dp0.3 4 dp0.4 5 dp0.5 6 dp0.6 40 2 s dp0.7 39 2 s dp1.0 41 dp1.1 38 dp1.2 37 dp1.3 36 dp1.4 34 dp1.5 23 dp1.6 22 dp1.7 9 vob 25 3 r vow3 24 3 r
october 1994 19 philips semiconductors product speci?cation 8-bit microcontrollers with osd and vst 84c44x; 84c64x; 84c84x 12 on screen display 12.1 features display format: 2 rows 16 characters software controlled vertical and horizontal display position 64 different (mask programmable) characters in rom black box background four programmable display character sizes four programmable character dot matrix sizes: C 6 9 and 6 13 C 8 9 and 8 13 half-dot rounding for the whole screen 4 from 7 colours possible on screen clock generator for on screen display function with: C rc oscillator C lc oscillator, for the various types of pca84c44x; 84c64x; 84c84x. 12.2 horizontal display position control the horizontal position counter is incremented every osd cycle after the programmed level of hsyncn occurs at the hsyncn pin. the counter is reset when the opposite polarity of the hsyncn pulse is reached. 12.3 vertical display position control the vertical position counter is incremented every hsyncn cycle and is reset by the vsyncn signal. 12.4 clock generator there are two types of oscillators available for the various types. the oscillator is triggered on the trailing edge of hsyncn when the osd logic is enabled and stops on the following leading edge of hsyncn. the osd oscillator must be externally adjusted to the desired frequency (decreasing the osd frequency gives broader characters). before the oscillation frequency can be adjusted hsyncn must be high (if hlvl = 1). oscillation stops by setting the hsyncn pin low when hlvl = 1. 12.4.1 rc oscillator the rc oscillator is available in the types: pca84c440; 84c443; 84c640; 84c643; 84c840; 84c843. the external rc network is connected between pin 28 and v ss (see fig.19). 12.4.2 lc oscillator the lc oscillator is available in the types: pca84c441; 84c444; 84c641; 84c644; 84c841; 84c844. the external lc network is connected between pins 28 and 29 (see fig.20).
october 1994 20 philips semiconductors product speci?cation 8-bit microcontrollers with osd and vst 84c44x; 84c64x; 84c84x handbook, full pagewidth horizontal display position control vertical display position control display control memory display character data memory clock generator control timing generator display control character rom hsyncn vsyncn vow3 vow2 vow1 vob mcd179 (1) fig.18 osd block diagram. (1) see figs 19 and 20 for connection of external components. handbook, halfpage v ss dd v r c dosc1 mcd173 fig.19 rc oscillator. fig.20 lc oscillator. handbook, halfpage mcd247 c1 dosc1 l1 c2 dosc2
october 1994 21 philips semiconductors product speci?cation 8-bit microcontrollers with osd and vst 84c44x; 84c64x; 84c84x 12.5 display data registers the display data registers consists of a group of 32 derivative registers located at addresses 20h to 3fh inclusive (see table 7). at power-up the contents of the display data registers are undefined. the format of each display data register is shown in table 8, and their functions described in table 9. table 7 display data registers addresses table 8 display data register (address 20h to 3fh) table 9 description of display data register bits 12.6 display control registers the display control registers consists of a group of 6 derivative registers located at addresses 40h to 45h inclusive (see table 10). each register may be read from or written to. after a reset operation the contents of the display control registers are zero. table 10 display control registers addresses address display data for bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 20h to 2fh row 0 = the ?rst display row cc1 cc0 md5 md4 md3 md2 md1 md0 30h to 3fh row 1 = the second display row 7 6 5 4 3 2 1 0 cc1 cc0 md5 md4 md3 md2 md1 md0 bit symbol function 7 cc1 colour code . the state of these two bits enable individual characters to be displayed in one of four colours. see tables 24, 25 and 26. 6 cc0 5 md5 character code . the character set is stored in rom and consists of 64 different characters. the selection of each character is dependent on the state of the 6 bits, md0 to md5. 4 md4 3 md3 2 md2 1 md1 0 md0 address register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 40h osdca cc34 cc24 cc14 rblk round stby vlvl hlvl 41h line 0a sz01 sz00 vp05 vp04 vp03 vp02 vp01 vp00 42h line 0b blk0 vb0 hp05 hp04 hp03 hp02 hp01 hp00 43h osdcb cdtw cdth cc33 cc23 cc32 cc12 cc21 cc11 44h line 1a sz11 sz10 vp15 vp14 vp13 vp12 vp11 vp10 45h line 1b blk1 vb1 hp15 hp14 hp13 hp12 hp11 hp10
october 1994 22 philips semiconductors product speci?cation 8-bit microcontrollers with osd and vst 84c44x; 84c64x; 84c84x 12.6.1 d erivative register osdca table 11 derivative register osdca (address 40h) table 12 description of oscda bits 7 6 5 4 3 2 1 0 cc34 cc24 cc14 rblk round stby vlvl hlvl bit symbol function 7 cc34 character colour code bits. these bits are used for colour selection purposes. see table 24. 6 cc24 5 cc14 4 rblk raster blanking control (see fig.24). when the rblk bit is: logic 1, the vob output is driven high to display the osd characters on a blank screen. logic 0, the vob output returns to its normal output state on the trailing edge of vsyncn. 3 round character rounding control (see figs 22 and 23). the rounding function generates half dots where the corners of two dots meet. the rounding function also works with multiple cell characters. when the round bit is: logic 1, the rounding function is enabled. logic 0, the rounding function is disabled. 2 stby stand-by. this bit is used to enable or disable the osd facility. when the stby bit is: logic 1, the osd oscillator is disabled. logic 0, the osd oscillator is enabled and the osd facility is available. 1 vlvl vertical synchronous signal level (see fig.21). this bit selects the active level of the vsyncn input signal. when the vlvl bit is: logic 1, vsyncn is active high. logic 0, vsyncn is active low. 0 hlvl horizontal synchronous signal level (see fig.21). this bit selects the active level of the hsyncn input signal. when the hlvl bit is: logic 1, hsyncn is active high. logic 0, hsyncn is active low. fig.21 vsyncn and hsyncn active level. handbook, full pagewidth (vsyncn) hsyncn (hlvl = vlvl = 0) (hlvl = vlvl = 1) characters can be displayed (vsyncn) hsyncn mcd180
october 1994 23 philips semiconductors product speci?cation 8-bit microcontrollers with osd and vst 84c44x; 84c64x; 84c84x fig.22 rounding function. handbook, full pagewidth round = 1 round = 0 t t t h h h t t t h h h mcd246 fig.23 rounding effect. handbook, halfpage mcd181 fig.24 raster blanking timing rlbk. handbook, full pagewidth mcd316 rblk vsyncn vob vow1, 2, 3 = normal output
october 1994 24 philips semiconductors product speci?cation 8-bit microcontrollers with osd and vst 84c44x; 84c64x; 84c84x 12.6.2 d erivative registers line 0a and line 0b table 13 derivative register line 0a (address 41h) table 14 description of line 0a bits table 15 derivative register line 0b (address 42h) table 16 description of line 0b bits register function line 0a determine the character size and vertical position of row 0 (the first display row). line 0b determine the horizontal position of row 0 and the selection of background and blanking functions. 7 6 5 4 3 2 1 0 sz01 sz00 vp05 vp04 vp03 vp02 vp01 vp00 bit symbol function 7 sz01 character size. the state of these two bits enable one of four possible character sizes to be selected for row 0. character sizes include background. see table 23. 6 sz00 5 vp05 vertical position control. the vertical position of row 0 is selected by the state of the 6 bits, vp00 to vp05. for details see section 12.7.1 vertical position. 4 vp04 3 vp03 2 vp02 1 vp01 0 vp00 7 6 5 4 3 2 1 0 blk0 vb0 hp05 hp04 hp03 hp02 hp01 hp00 bit symbol function 7 blk0 blanking . this bit enables or disables the character display. when blk0 is set to: logic 1, the outputs vow1, vow2, vow3 and vob are enabled; characters are displayed. logic 0, the outputs vow1, vow2, vow3 and vob are disabled; no characters are displayed. 6 vb0 background. this bit determines whether the background display is selected or not. the visual effect of background versus no background is shown in fig.26. when vb0 is set to: logic 1, the characters in this row are displayed with background. logic 0, the background is disabled and only the characters are displayed. 5 hp05 horizontal position control . these 6 bits determine the start position of row 0. the horizontal position control is only active during osdc clock cycles. for details section 12.7.2 horizontal position and fig.25. 4 hp04 3 hp03 2 hp02 1 hp01 0 hp00
october 1994 25 philips semiconductors product speci?cation 8-bit microcontrollers with osd and vst 84c44x; 84c64x; 84c84x 12.6.3 d erivative registers line 1a and line 1b table 17 derivative register line 1a (address 44h) table 18 description of line 1a bits table 19 derivative register line 1b (address 45h) table 20 description of line 1b bits register function line 1a determine the character size and vertical position of row 1 (the second display row). line 1b determine the horizontal position of row 1 and the selection of background and blanking functions. 7 6 5 4 3 2 1 0 sz11 sz10 vp15 vp14 vp13 vp12 vp11 vp10 bit symbol function 7 sz11 character size. the state of these two bits enable one of four possible character sizes to be selected for row 1. character sizes include background. see table 23. 6 sz10 5 vp15 vertical position control. the vertical position of row 1 is selected by the state of the 6 bits, vp10 to vp15. for details see section 12.7.1 vertical position. 4 vp14 3 vp13 2 vp12 1 vp11 0 vp10 7 6 5 4 3 2 1 0 blk1 vb1 hp15 hp14 hp13 hp12 hp11 hp10 bit symbol function 7 blk1 blanking. this bit enables or disables the character display. when blk1 is: logic 0, the outputs vow1, vow2, vow3 and vob are disabled; no characters are displayed. logic 1, the outputs vow1, vow2, vow3 and vob are enabled; characters are displayed. 6 vb1 background . this bit determines whether the background display is selected or not. the visual effect of background versus no background is shown in fig.26. when vb1 is set to: logic 1, the characters in this line are displayed with background. logic 0, the background is disabled and only the character is displayed. 5 hp15 horizontal position control . these 6 bits determine the start position of row 1. the horizontal position control is only active during osdc clock cycles. for details section 12.7.2 horizontal position and fig.25. 4 hp14 3 hp13 2 hp12 1 hp11 0 hp10
october 1994 26 philips semiconductors product speci?cation 8-bit microcontrollers with osd and vst 84c44x; 84c64x; 84c84x 12.6.4 d erivative register osdcb table 21 derivative register osdcb (address 43h) table 22 description of osdcb bits register function osdcb determine the selection of: the size of the dot matrix grid four colours from a possible seven for the display. 7 6 5 4 3 2 1 0 cdtw cdth cc33 cc23 cc32 cc12 cc21 cc11 bit symbol function 7 cdtw character dot width control .the state of this bit determines the dot width of the character. when the cdtw bit is set to: logic 1, the character width is 6 dots. logic 0, the character width is 8 dots. 6 cdth character dot height control . the state of this bit determines the dot height of the character . when the cdth bit is set to: logic 1, the character height is 13 dots. logic 0, the character height is 9 dots. 5 cc33 colour control bits. in every vsyncn cycle one screen can select any 4 colours from 7 and in addition a blank or black screen. combinations of cc1x, cc2x and cc3x control the character outputs vow1, vow2 and vow3 as shown in table 24. 4 cc23 3 cc32 2 cc12 1 cc21 0 cc11
october 1994 27 philips semiconductors product speci?cation 8-bit microcontrollers with osd and vst 84c44x; 84c64x; 84c84x 12.7 osd display position 12.7.1 v ertical position the line number of the vertical start position for: row 0 is 4 (vp00 ? vp05) row 1 is 4 (vp10 ? vp15). where: (vp00 ? vp05) = the decimal value of vp00 ? vp05 (vp10 ? vp15) = the decimal value of vp10 ? vp15. the character height in: row 0 is h0 and is a function of the number of dots per character and the state of the size control bits sz00 and sz01 row 1 is h1 and is a function of the number of dots per character and the state of the size control bits sz10 and sz11. row 0 and row 1 must not overlap each other and therefore: vp1 3 (vp0 + h0); see fig.25. the four possible character heights are shown in table 23. 12.7.2 h orizontal position the horizontal start position (hp) of, row 0: row 1: where: (hp00 ? hp05) = the decimal value of hp00 ? hp05 and (hp00 ? hp05) > 10 (hp10 ? hp15) = the decimal value of hp10 ? hp15 and (hp10 ? hp15) > 10 t oscd = one oscd clock period. therefore for both row 0 and row 1, hp0, hp1 3 45 t oscd . hp0 4 hp00 hp05 ? ( ) 5 t oscd + = hp1 4 hp10 hp15 ? ( ) 5 t oscd + = handbook, full pagewidth row 0 characters vp0 hp0 h0 hp1 vp1 mcd183 row 1 characters fig.25 display position. fig.26 background versus no background. handbook, halfpage with background without background mcd182
october 1994 28 philips semiconductors product speci?cation 8-bit microcontrollers with osd and vst 84c44x; 84c64x; 84c84x 12.8 osd character size and colour selection 12.8.1 c haracter size the character sizes are determined by the bits: cdtw, for the width cdth, for the height. the character sizes are selected by bits szn1 and szn0, which denotes: sz01 and sz00 for row 0 sz11 and sz10 for row 1. table 23 character sizes selection h denotes one horizontal line, t denotes one osdc clock period and d denotes dots per character width/height. size bits character size dot matrix point szn1 szn0 vertical horizontal vertical horizontal 9d 13d 6d 8d 0 0 18h 26h 12t 16t 2h 2t 0 1 36h 52h 24t 32t 4h 4t 1 0 54h 78h 36t 48t 6h 6t 1 1 72h 104h 48t 64t 8h 8t 12.8.2 c olour selection colour selection is achieved using bits in the, osdca register: cc34, cc24 and cc14 osdcb register: cc33, cc23, cc32, cc12, cc21, and cc11 display data registers: cc1 and cc0. in this way every combination of four colours can be made (black and white can not be displayed at the same time). the user may choose one colour out of each block. table 24 shows the selection of the output combinations. tables 25 and 26 show the possible colour combinations. fig.27 colour control. handbook, full pagewidth character rom display data memory display circuit control registers vow3 vob or cc1 cc0 ccxx dot background control vow2 vow1 mcd184 output control logic
october 1994 29 philips semiconductors product speci?cation 8-bit microcontrollers with osd and vst 84c44x; 84c64x; 84c84x table 24 character colour control table 25 possible colour combinations table 26 possible colour combinations (continued) colour code character output pins1 cc1 cc0 vow1 (red) vow2 (green) vow3 (blue) 0 0 cc11 cc21 cc1 1 + cc21 0 1 cc12 cc12 + cc32 cc32 1 0 cc23 + cc33 cc23 cc33 1 1 cc14 cc24 cc34 colour (cc1, cc0) = (0, 0) (cc1, cc0) = (0, 1) (cc1, cc0) = (1, 0) vow1 vow2 vow3 vow1 vow2 vow3 vow1 vow2 vow3 cc11 cc21 cc1 1+cc21 cc12 cc12+cc32 cc32 cc12 cc12+cc32 cc32 blue 0 0 1 0 0 1 0 0 1 green 0 1 0 0 1 0 0 1 0 red 1 0 0 1 0 0 1 0 0 yellow 1 1 0 - - - - - - magenta - - - 1 0 1 - - - cyan - - - - - - 0 1 1 colour (cc1, cc0) = (1, 1) vow1 vow2 vow3 cc14 cc24 cc34 blue 0 0 1 green 0 1 0 red 1 0 0 yellow 1 1 0 magenta 1 0 1 cyan 0 1 1 white 1 1 1 black 0 0 0
october 1994 30 philips semiconductors product speci?cation 8-bit microcontrollers with osd and vst 84c44x; 84c64x; 84c84x 12.9 character rom character rom contains the dot character fonts. 13 x 8 dots are reserved for each character, regardless of the dot matrix size actually selected. the dot matrix grid is shown in fig.28. philips provides a software under ms dos environment (ibm/pc or compatible) to help customer to design the character font on the screen and to generate the bit pattern hex decimal file automatically. contact your local philips sales organization for details. handbook, halfpage mcd185 1 2 3 4 5 6 7 8 13 12 10 9 1 2 3 4 5 6 7 8 11 fig.28 character rom. 13 emulation mode the emulation mode configuration is shown in fig.29. in the emulation mode configuration the pca84c640's cpu is disabled and only its derivative logic is active. the device is controlled by the pcf84c00 bond-out chip. the pca84c640's two derivative ports act as additional ports for the pcf84c00. the interaction between the two devices is as follows: 1. during the first machine cycle the pcf84c00 fetches an instruction from eprom and then decodes that instruction. 2. during the second machine cycle the pcf84c00 executes the decoded instruction. if the instruction is related to the derivative ports then dxale, dxrdn and/or dxwrn become active and the pca84c640 operates as a peripheral of the pcf84c00. 3. depending on the type of instruction executed during the second machine cycle the following data transfer happens: a) during ts1 data from the eprom is available on p0.0 to p0.7 which is then available on ib0.0 of the pcf84c00. b) during ts4 data from the pca84c640 can be transferred to the pcf84c00. c) during ts6 data from the pcf84c00 can be transferred to the pca84c640.
october 1994 31 philips semiconductors product speci?cation 8-bit microcontrollers with osd and vst 84c44x; 84c64x; 84c84x handbook, full pagewidth p1.0 dp0.0 - dp0.7 p0.0 - p0.7 xtal1 reset xtal2 stff dxale dxrd dxwr a0 - a12 d0 - d7 psen a0 - a12 d0 - d7 address bus data bus ce p1.0 - p1.7 p2.0 - p2.7 p1.1 p0.0 - p0.7 p1.2 dp1.0 - dp1.7 p1.3 xtal1 reset pcf84c00 pca84c640 eprom mcd317 test/emu + 5v fig.29 emulation mode configuration.
october 1994 32 philips semiconductors product speci?cation 8-bit microcontrollers with osd and vst 84c44x; 84c64x; 84c84x 14 register map the number within parentheses denotes the initial state; x denotes dont care. r = read, w = write, r/w =read/write. addr reg bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w 00h dp0 (pin) dp0.7 (x) dp0.6 (x) dp0.5 (x) dp0.4 (x) dp0.3 (x) dp0.2 (x) dp0.1 (x) dp0.0 (x) r 01h dp1 (pin) dp1.7 (x) dp1.6 (x) dp1.5 (x) dp1.4 (1) (x) dp1.3 (x) dp1.2 (x) dp1.1 (x) dp1.0 (x) r 02h dp0r (latch) dp0.7 (1) dp0.6 (1) dp0.5 (1) dp0.4 (1) dp0.3 (1) dp0.2 (1) dp0.1 (1) dp0.0 (1) r/w 03h dp1r (latch) dp1.7 (1) dp1.6 (1) dp1.5 (1) dp1.4 (1) (1) dp1.3 (1) dp1.2 (1) dp1.1 (1) dp1.0 (1) r/w 10h pwm1 - - pwm15 (0) pwm14 (0) pwm13 (0) pwm12 (0) pwm11 (0) pwm10 (0) r/w 11h pwm2 - - pwm25 (0) pwm24 (0) pwm23 (0) pwm22 (0) pwm21 (0) pwm20 (0) r/w 12h pwm3 - - pwm35 (0) pwm34 (0) pwm33 (0) pwm32 (0) pwm31 (0) pwm30 (0) r/w 13h pwm4 - - pwm45 (0) pwm44 (0) pwm43 (0) pwm42 (0) pwm41 (0) pwm40 (0) r/w 14h pwm5 - - pwm55 (0) pwm54 (0) pwm53 (0) pwm52 (0) pwm51 (0) pwm50 (0) r/w 15h vstl - vst06 (0) vst05 (0) vst04 (0) vst03 (0) vst02 (0) vst01 (0) vst00 (0) r/w 16h vsth - vst13 (0) vst12 (0) vst11 (0) vst10 (0) vst09 (0) vst08 (0) vst07 (0) r/w 17h afco - - - - - afc2 (0) afc1 (0) afc0 (0) r/w 18h afcc - - - - - - - afcc (x) r/w 19h dp0e/ pwme scle (0) sdae (0) pwm5e (0) pwm4e (0) pwm3e (0) pwm2e (0) pwm1e (0) tdace (0) r/w 1ah dp1e/ pwmlvl - - - afce (0) p14lvl (0) p6lvl (0) vow2e (0) vow1e (0) r/w 20h to 3fh data display memory cc1 (x) cc0 (x) md5 (x) md4 (x) md3 (x) md2 (x) md1 (x) md0 (x) w
october 1994 33 philips semiconductors product speci?cation 8-bit microcontrollers with osd and vst 84c44x; 84c64x; 84c84x note 1. these bits are not available in the pca84c441, pca84c444, pca84c641, pca84c644, pca84c841 and pca84c844. 15 limiting values in accordance with the absolute maximum rating system (iec 134). 40h osdca cc34 (0) cc24 (0) cc14 (0) rblk (0) round (0) stby (1) vlvl (0) hlvl (0) r/w 41h line0a sz01 (0) sz00 (0) vp05 (0) vp04 (0) vp03 (0) vp02 (0) vp01 (0) vp00 (0) r/w 42h line0b blk0 (0) vb0 (0) hp05 (0) hp04 (0) hp03 (0) hp02 (1) hp01 (0) hp00 (0) r/w 43h osdcb cdtv (0) cdth (0) cc33 (0) cc23 (0) cc32 (0) cc12 (1) cc21 (0) ccv11 (0) r/w 44h line1a sz11 (0) sz10 (0) vp15 (0) vp14 (0) vp13 (0) vp12 (1) vp11 (0) vp10 (0) r/w 45h line1b blk1 (0) vb1 (0) hp15 (0) hp14 (0) hp13 (0) hp12 (1) hp11 (0) hp10 (0) r/w symbol parameter min. max. unit v dd supply voltage - 0.3 +7.0 v v i input voltage (all inputs) - 0.3 v dd + 0.3 v i oh maximum source current for all port lines - - 10 ma i ol maximum sink current for all port lines - - 30 ma p tot total power dissipation - 900 mw t stg storage temperature - 55 +125 c t amb operating ambient temperature (for all devices) - 20 +70 c addr reg bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w
october 1994 34 philips semiconductors product speci?cation 8-bit microcontrollers with osd and vst 84c44x; 84c64x; 84c84x 16 dc characteristics v dd = 4.5 v to 5.5 v; v ss = 0 v; t amb = - 20 to +70 c; all voltages with respect to v ss unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supply v dd operating supply voltage 4.5 5.0 5.5 v i dd operating supply current f osdcrc = f osdclc = f xta l ; v dd = 5 v; see note 1; f xtal = 10 mhz - 5 10 ma f xtal = 6 mhz - 3.5 8 ma f osdcrc = f osdclc = st op; v dd = 5 v; see note 1; - f xtal = 10 mhz - 3 7 ma f xtal = 6 mhz - 1.5 3.5 ma i dd(id) supply current idle mode v dd = 5 v; f xtal = 10 mhz - 1.3 3 ma f xtal = 6 mhz; see note 1 - 0.8 1.5 ma i dd(st) supply current stop mode v dd = 5.5 v; see notes 1 and 2 - 5 10 m a inputs i ih high level input current (pin reset) v in = 0.5 v 20 - - m a p orts p0, p1, dp0, dp1, hsyncn and vsyncn v il low level input voltage 0 - 0.3v dd v v ih high level input voltage 0.7v dd - v dd v p orts p0, p1, dp0, dp1, intn/t0 and t1 i ll input leakage current v ss < v i < v dd ports p0, p1, dp0 and dp1 - - 10 m a ports intn/t0 and t1 0.01 0.2 10 m a outputs: ports p0, p1, dp0, dp1; vob and vow3 (see figs 30, 31 and 31) i ol low level output sink current port p0 v o = 1.2 v 10 - - ma ports p1, dp0 and dp1 v o = 0.4 v 5 10 - ma ports vob and vow3 v o = 0.4 v 1.2 3 - ma p orts p0, p1, dp0 and dp1 (see figs 33 and 33) i oh high level pull-up output source current v o = v ss - 140 400 m a v o = 0.7v dd 40 100 - m a high level push-pull output source current v o = v dd - 0.4 v 3 7 - ma o utputs vob and vow3 (see fig.33) i oh high level push-pull output source current v o = v dd - 0.4 v 1.2 3 - ma
october 1994 35 philips semiconductors product speci?cation 8-bit microcontrollers with osd and vst 84c44x; 84c64x; 84c84x notes 1. v il = v ss ; v ih = v dd ; all outputs and sense input lines unloaded. all open drain ports connected to v ss . 2. crystal is connected between xtal1 and xtal2; t1 = v ss ; int/t0 = v dd . 17 ac characteristics v dd = 5 v; t amb = - 20 to +70 c; all voltages with respect to v ss ; unless otherwise speci?ed. note 1. oscillator with three (3) options for optimum use. afc characteristics; port dp1.7/afc v ai comparator analog input voltage v ss - v dd v v ae conversion error range - - 0.5 lsb symbol parameter conditions min. typ. max. unit oscillator f xtal crystal frequency; note 1 1 - 10.0 mhz f osc-xtal oscillator frequency; option 1 g m = 0.4 ms (typ.) 1 - 6.0 mhz f osc-pxe not allowed mhz f osc-xtal oscillator frequency; option 2 g m = 1.6 ms (typ.) 4.0 - 10.0 mhz f osc-pxe 1.0 - 6.0 mhz f osc-xtal oscillator frequency; option 3 g m = 4.5 ms (typ.) not allowed mhz f osc-pxe 3.0 - 10.0 mhz c xtal1 external capacitance at xtal1 with xtal resonator not required pf with pxe resonator - 30 100 pf c xtal2 external capacitance at xtal2 with xtal resonator not required pf with pxe resonator - 30 100 pf f dosc on-screen-display clock frequency 4.0 8.0 10.0 mhz symbol parameter conditions min. typ. max. unit
october 1994 36 philips semiconductors product speci?cation 8-bit microcontrollers with osd and vst 84c44x; 84c64x; 84c84x 17.1 characteristic curves fig.30 typical low level output sink current as a function of the supply voltage. port p0 ; v o = 1.2 v. (1) t amb = - 20 c. (2) t amb = 25 c. (3) t amb = 80 c. handbook, halfpage 0 2 4 6 40 4 16 28 34 10 22 mlc004 i ol (ma) v (v) dd (3) (2) (1) handbook, halfpage 0 2 4 6 10 0 8 mlb999 6 4 2 i ol (ma) v (v) dd (3) (2) (1) fig.31 typical low level output sink current as a function of the supply voltage. ports p1, dp0 and dp1 ; v o = 0.4 v. (1) t amb = - 20 c. (2) t amb = 25 c. (3) t amb = 80 c. handbook, halfpage 0 2 4 6 10 0 8 mlc002 6 4 2 i ol (ma) v (v) dd (3) (2) (1) outputs vow1, vow2, vow3 and vob ; v o = 0.4 v. (1) t amb = - 20 c. (2) t amb = 25 c. (3) t amb = 80 c. fig.32 typical low level output sink current as a function of the supply voltage. handbook, halfpage 0 2 4 6 200 0 160 mlc001 120 80 40 i oh (ma) v (v) dd (3) (2) (1) fig.33 typical high level pull-up output source current as a function of the supply voltage. ports p0, p1, dp0 and dp1 ; v o = v ss . (1) t amb = - 20 c. (2) t amb = 25 c. (3) t amb = 80 c.
october 1994 37 philips semiconductors product speci?cation 8-bit microcontrollers with osd and vst 84c44x; 84c64x; 84c84x handbook, halfpage 0 2 4 6 mlc005 v (v) dd (3) (2) (1) 200 0 160 120 80 40 i oh (ma) ports p0, p1, dp0 and dp1 ; v o = 0.7v dd . (1) t amb = - 20 c. (2) t amb = 25 c. (3) t amb = 80 c. fig.34 typical high level pull-up output source current as a function of the supply voltage. handbook, halfpage 0 2 4 6 5 4 2 1 0 3 mlc003 i oh (ma) v (v) dd (3) (2) (1) fig.35 typical high level pull-up output source current as a function of the supply voltage. outputs vow1, vow2, vow3 and vob ; v o = v dd - 0.4 v. (1) t amb = - 20 c. (2) t amb = 25 c. (3) t amb = 80 c.
october 1994 38 philips semiconductors product speci?cation 8-bit microcontrollers with osd and vst 84c44x; 84c64x; 84c84x 18 package outline fig.36 plastic shrink dual in-line package; 42 leads (600 mil); sdip42 (sot270-1). handbook, full pagewidth 1 22 21 1.3 max 14.1 13.7 4.57 max 5.08 max 0.51 min 3.2 2.9 seating plane 0.18 m 0.53 max 1.778 (40x) 1.73 max 15.80 15.24 0.32 max 15.24 17.15 15.90 msa268 - 1 42 39.0 38.4 dimensions in mm.
october 1994 39 philips semiconductors product speci?cation 8-bit microcontrollers with osd and vst 84c44x; 84c64x; 84c84x 19 soldering 19.1 plastic dual in-line packages 19.1.1 b y dip or wave the maximum permissible temperature of the solder is 260 c; this temperature must not be in contact with the joint for more than 5 s. the total contact time of successive solder waves must not exceed 5 s. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified storage maximum. if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 19.1.2 r epairing soldered joints apply a low voltage soldering iron below the seating plane (or not more than 2 mm above it). if its temperature is below 300 c, it must not be in contact for more than 10 s; if between 300 and 400 c, for not more than 5 s. 20 definitions 21 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 22 purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.

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